The manufacture of a DRAM memory cell includes the fabrication of a transistor, a capacitor and contacts to periphery circuits. To shrink the area of the devices in the DRAM cell is one of the most important issues for the designer of DRAM memory. With the advent of ULSI DRAM devices, the size of the memory cells becomes smaller and smaller such that the area available for a single memory cell has become exceedingly small.
Additionally, because the step height of a stacked capacitor is too large for large-scale semiconductor devices, a multi-level contact for the periphery circuit is widely used. Further, the self aligned contact must be used in ULSI products. However, when there is no need to use self aligned contact technology, the spacer and the cap of the gate electrode can be formed of TEOS oxide.
Referring to FIG. 1, a plurality of multi-level contact holes are formed. A silicon substrate 9 provides the base for the semiconductor devices. A plate poly layer 10 is connected to a capacitor 11 of the semiconductor device, and a bit line 13 includes a first tungsten silicide layer 13a and a first polysilicon layer 13b. The word line 17 includes an oxide cap 17a, an oxide spacer 17b, a second tungsten silicide layer 17c, and a second polysilicon layer 17d. The bit line 13 and the word line 17 are used to address the memory cell. A plurality of multi-level contact holes 18 are formed by penetrating a BPSG layer 19 using the developed photoresist layer 20 as a mask. Because the integration of the semiconductor device mentioned above is not high, it is unnecessary to utilize a self aligned contact and an antireflection layer. Thus, the multi-level contact holes can be formed in an etching step using fluorine containing gas as a etchant.
When a large scale integration product is to be fabricated, an anti-reflection layer must be used to increase the cell density and improve the photo proximity effect. The inorganic anti-reflection layer is typically composed of silicon nitride (Si.sub.3 N.sub.4) or silicon oxynitride (SiON). In addition, self aligned contact technology is used to increase critical dimension control. Thus, the material used to form the spacer and the cap of the gate electrode is changed to silicon nitride (Si.sub.3 N.sub.4).
Turning to FIG. 2, a silicon substrate 29 provides a base for the large scale semiconductor devices. A plate poly layer 30 is connected to a capacitor 31 of the large scale semiconductor device, and the bit line 33 includes a first tungsten silicide layer 33a, a first poly silicon layer 33b, and a silicon oxynitride layer 33c. The silicon oxynitride layer 33c, which can also be a Si3N4 layer on the first tungsten silicide layer 33a is used as an anti-reflection layer or an etching hardmask. The word line 37 includes a silicon nitride layer 37a, a silicon nitride spacer 37b, a second tungsten silicide layer 37c, and a second polysilicon layer 37d. The bit line 33 and the word line 37 are used to address the semiconductor device. Subsequently, to form the multi-level contact, a photoresist layer 38 is developed on the BPSG layer 39.
When a traditional etching process 40 is used to form the multi-level contact holes 41, the etching process 40 tends to result in etch-stop/polymer regrowth on the silicon nitride layer 37a and the silicon oxynitride layer 33c. Thus, contact is not made to the underlying conductive layers. Further, the photoresist selectivity is poor. As shown in FIG. 3, the tungsten silicide layer 33a and the second tungsten silicide layer 37c are not exposed. Further, the etching tends to over etch the plate poly layer 30 and the silicon substrate 29 when a traditional etching process 40 such as CF.sub.4 or C.sub.4 H.sub.8 +CO is used.
What is needed is a new etching process that will etch through the silicon nitride layers and silicon oxynitride layers without poor photoresist loss for controlling the critical dimension of the semiconductor process.